Open Memory Interface Webinar – hosted by OpenCAPI Consortium

March 25, 2021 – 12:00 – 2:00 pm Eastern Time/9:00 – 11:00 am Pacific Time/5:00 – 7:00 pm GMT


In this webinar you will hear the latest on memory disaggregation research trends and applications from researchers in industry and academia. The concept of memory disaggregation has been around for a while now. However, it only recently took-off generating wide interest.  A combination between more integrated support in CPUs (e.g., OpenCAPI coherent attachment and IBM’s POWER10 with Memory Inception) and new applications requiring unprecedented amounts of memory have made this technology an appealing solution. Applications of memory disaggregation are spanning from big-data and in memory-databases, to a tool for optimizing utilization and minimizing costs in a data center.

Organizers: Christian Pinto (Research Scientist, IBM), Peter H Hofstee (Distinguished RSM, IBM)

Slot 1

  • Duration: 5 minutes 
  • Title: Welcome/Intro/Speakers presentation

Slot 2

  • Duration: 20 minutes
  • Speaker: Allan Cantle (CEO, Nallasway)
  • Title:  OMI, The missing piece of a Modular, Flexible and Composable Computing World. 
  • Abstract: As our industry inexorably shifts towards a more Data-Centric world there is a growing need for building in the flexibility of Domain-Specific Architectures by disaggregating the component parts including Memory. However Local DDR Memory, with its Low Latency and High Bandwidth requirements does not lend itself to easy disaggregation today. OMI Successfully addresses this challenge by aligning the Memory IO to use the same SerDes Transceiver technology of all other Computing components. This presentation highlights the many advantages of OMI and introduces Open HPC implementation Concepts that demonstrate the Modular, Flexible and Composable possibilities that can be achieved when utilizing OMI attached Memory. 
  • Bio: Allan Cantle is CEO of Nallasway, consulting on Heterogeneous, High-Performance Computing Solutions. He is also the OpenCAPI Consortium Technical Director and Board Advisor.  Previously, Allan was the founder of Nallatech, which, during his 25-year tenure, became widely known as a pioneer in FPGA Accelerated Computing. Before founding Nallatech; Allan was an Electronics Systems Engineer at BAE Systems, developing real-time heterogeneous high-performance computers. He holds a degree in Electrical and Electronics Engineering from the University of Plymouth

Slot 3

  • Duration: 20 minutes
  • Speaker: Steven Roberts (STSM, IBM)
  • Title:  OpenCAPI with Power10 Memory Inception
  • Abstract: Power10 introduces an embedded AFU for host-to-host communication over OpenCAPI links.  The resultant hardware logic and use cases we term as Memory Inception.  This presentation illustrates how OpenCAPI LPC reference design is implemented with Power10 as both a host and a target.  Lastly, we review the use cases motivating this capability.
  • Bio: Steven Roberts is a Solutions Architect with IBM Cognitive Systems with the responsibility to aid the adoption of emerging technologies.  Recently has served as the system architect for seven systems that have debuted in the SuperComputer Top 500 list and served as Chief Engineer for Summit and Sierra.  Currently, he is engaged in OpenCAPI and CXL project system prototypes and problem identification efforts for the next frontier of system challenges.

Slot 4 

  • Duration: 20 minutes
  • Speaker: Felix Eberhardt (Hasso Plattner Institute, Germany)
  • Title: Impacts of Disaggregated Memory on OS and Applications
  • Abstract: Disaggregation of system resources offers various benefits, such as flexibility of provisioning, consolidation of workloads, offering higher limits for bursts of resource consumption. With ThymesisFlow an OpenCAPI-based memory disaggregation prototype is already available to experiment with. Several research questions arise with this new system architecture. In this talk, we briefly tackle new challenges and the impacts on Operating Systems and Applications. We will present a case for new memory placement considerations and show the first results of performance impacts on challenging workloads, such as In-Memory Databases.
  • Bio : Felix Eberhardt is a researcher at the Operating Systems and Middleware Chair of Prof. Andreas Polze at the Hasso Plattner Institute in Potsdam. His research interests are performance analysis and optimization for workloads in scale-up systems. He was part of the initial port of SAP HANA to Power and participated in several industry projects with IBM, SAP, and in a European project (SSICLOPS).

Slot 5

  • Duration: 20 minutes
  • Speaker: Ákos Hadnagy (Delft University of Technology, Netherlands)
  • Title: Enabling High Volume-Low-Cost Disaggregated Memory for Big Data Analytics
  • Abstract: Big data analytics is not only a compute-intensive application domain, but it is also becoming increasingly memory-intensive. At the massive scale, these applications are deployed, provisioning memory resources is a complex task, and frequently wasteful due to the fact that these resources are tied to individual nodes. The allocated memory resources have to satisfy the peak requirements of the application, while the application has to be responsible to distribute and communicate the data required by each node. The current way of selecting the node types in a cloud environment is an elaborate optimization problem whilst skipping this step results in increased costs and under-utilized cloud resources. In this talk, we discuss how Memory Inception can be a game-changer for big data workloads due to its ability to pool physical memory across multiple nodes in a variety of configurations. We show that specific characteristics of big data frameworks, such as immutable data types, enable easy integration and utilization of the Memory Inception infrastructure. We also discuss possible application alternatives that could benefit from using such a system and our prototyping infrastructure that uses ThymesisFlow on our existing Power9 system.
  • Bio: Ákos Hadnagy is a researcher at TU Delft. He received his BSc in Electrical Engineering from the Budapest University of Technology and Economics in 2018, and his MSc in Computer Engineering from the Delft University of Technology in 2020. His research interests include high-level digital design, hardware acceleration, and heterogeneous computer architectures.

Slot 6

  • 20 minutes – Q&A
  • 5 minutes – Closing remarks