A Statement from the OpenCAPI Consortium Leadership
As announced on August 1, 2022 at the Flash Memory Summit, the OpenCAPITM Consortium (OCC) and Compute Express LinkTM (CXL) Consortium entered an agreement, which if approved and agreed upon by all parties, would transfer the OpenCAPI and Open Memory Interface (OMI) specifications and other OCC assets to the CXL Consortium.
The members of both consortiums agreed that the transfer would take place September 15, 2022. Upon completion of the asset transfer, OCC will finalize operations and dissolve. OCC member companies in good standing will be contacted with details of their specific membership benefits in CXL.
The OCC leadership extends its gratitude to its members and supporters for six years of effort producing the specifications for a cache-coherent interconnect for processors, memory expansion, accelerators and for a serial attached near memory interface providing for low latency and high bandwidth connections to main memory (OMI).
We are excited to witness the industry coming together around one organization to drive open innovation. We expect this will yield the finest business results for the industry and for the members of the consortia.
Bob Szabo, OpenCAPI Consortium President
About the CXL™ Consortium
The CXL Consortium is an industry standards body dedicated to advancing Compute Express Link™
(CXL™) technology. CXL is a high-speed interconnect offering coherency and memory semantics using
high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators,
memory buffers, and smart I/O devices. For more information or to join, visit www.computeexpresslink.org.
VISIT CXL CONSORTIUM FOR MORE
OpenCAPI Workshop – Transitioning Local Memory from DDR to the OMI Interface
Flash Memory Summit 2022 – August 1, 2022
Thank you for visiting the OpenCAPI Consortium Booth #651 at FMS 2022!
Webinar: Latest Trends in Memory Disaggregation
In case you missed this informative event, or you would like to review for reference or further listening, please click on the following links:
March 25, 2021 – 12:00 – 2:00 pm Eastern Time/9:00 – 11:00 am Pacific Time/4:00 – 6:00 pm GMT
In this webinar, you heard about the latest on memory disaggregation research trends and applications from researchers in industry and academia. The concept of memory disaggregation has been around for a while now. However, it only recently took-off generating wide interest. A combination between more integrated support in CPUs (e.g., OpenCAPI coherent attachment and IBM’s POWER10 with Memory Inception) and new applications requiring unprecedented amounts of memory have made this technology an appealing solution. Applications of memory disaggregation are spanning from big-data and in memory-databases, to a tool for optimizing utilization and minimizing costs in a data-center.
Check out these downloadable specifications for public learning purposes!
OpenCAPI 3.0 Transaction Layer Specification
OpenCAPI 3.1 Transaction Layer Specification
OpenCAPI 4.0 Transaction Layer Specification
OpenCAPI Data Link Layer Specification
OpenCAPI 32Gbps PHY Signaling Specification
OpenCAPI 32Gbps PHY Mechanical Specification
OpenCAPI 25 Gbps PHY Mechanical Specification
OpenCAPI 25 Gbps PHY Signaling Specification
OpenCAPI Discovery and Configuration Architecture Specification
Fill out the form “Download the Standard” at the bottom of this page to download the specifications.
Attention Members Only – See all approved specifications.
Please click on the member login and view the All Members documents.
The OpenCAPI Ready™ program is used by the OpenCAPI Consortium to enable OpenCAPI ecosystem product developers to indicate that a product has been shown/demonstrated to meet a minimum set of characteristics and should be interoperable with other OpenCAPI Ready products.
Click here to submit your product: OpenCAPI Ready Submission